We are not able to run our dual GEM config. However, eth1 still doesn’t work correctly. I don’t have the Marvell datasheet handy, but recall seeing that when run a 1. Thanks for the advice. Did you try running ping with u-boot? Cadence GEM rev 0x at 0xec irq
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net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]
Add mdio in the top level: The device tree in the newer kernels uses the MACB drivers. Please upgrade to a Xilinx. I haven’t used Zynq before, so maybe this suggestion is not marvel.
Patch is applicable ONLY to the pny I assume you use the same interface voltage for both PHY chips. Reluctant to pursue it as we are not using Petalinux:. We have tried to apply the patch, but does’nt works I’ve tried your device tree example as well as different examples found:.
Auto-suggest helps you quickly narrow down your limux results by suggesting possible matches as you type. I suspect this is a software issue. I Have met the same problem, hope could get some ideas from you!
The state machine for this is pretty simple and basically counts the bits as they go out and just inverts the value for one bit period during the desired address bit for example bit 1. Link never comes up on eth1, although I can see received packets on the eth1 interface, as if the default PHY configuration is enough to receive packets in some form. I have tried the current xilinx-linux git repo, and the patch is not in that repo, nor is the patch applicable to that repo.
Marvell Phy () issue since v kernel – Patchwork
Liunx you explain how to implement Xilinx provided patch at each these different steps? Thanks for the advice. Add the phy handle to the gem sections: I will post when I get the new release and test it.
Do you have any further information phj this question? Check the reset pin to the PHYs. It will be fixed in the ChromeFirefoxInternet Explorer 11Safari. I will dig into the phy initialization code to see why it seems to ignore PHY1. Yes, I have tried it, but eth1 still doesn’t work. When we get back to the issue I will post whatever resolution we come up with.
I’ve tried your device tree example as well as different examples found: We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. Cadence GEM rev 0x at 0xeb irq What other kernel settings did you have lijux enable to allow the Marvell 88e PHY to have the correct drivers from petalinux?
According to a Xilinx FAE: Note that I am using two different sub-nets – the Note that it attaches a Generic PHY driver to eth1, and the phy id is: This file is automatically generated by Xilinx. Verified fix for this problem.
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